Model - based HW / SW inline IPSec microarchitectural design and validation using

In this paper, a team of Intel networking engineers presents a flow used to design and validate the microarchitecture of a new packet-processing module for Intel® chipsets, based on models captured using Intel® CoFluentTM Studio (CoFluentTM). With this design and validation flow, the team created an executable specification of the new packet processing module. The team first validated the functional behavior and the performance of the module for different use cases. The executable specification (a CoFluent model) helped identify and solve architectural issues before and during hardware/software development. The team then reused the same CoFluent model as a device model in order to accelerate the development of software in a Wind River Simics* virtual platform. “Our design flow, based on Intel® CoFluentTM Studio models, enabled us to validate our complete product solution requirement from the SW application level down to microarchitecture, and do this early in the design cycle.” – Andrew Cunningham, Senior Digital Design Engineer, Intel Corporation Andrew Cunningham Intel Corporation Patrick Fleming Intel Corporation Jérôme Lemaitre Intel Corporation Ireneusz Sobanski Intel Corporation Chris M. Wolf Intel Corporation Background IPSec is a standard network protocol used to securely transfer packets over the Internet. To cope with today’s stronger requirements for network security, the cryptographic algorithms of the IPSec protocol require more computing power and system bandwidth. However, when run on a CPU, these algorithms/tasks require so much computing power and system bandwidth that they can reduce the performance of the network connection. To avoid this situation, we can reduce the load placed on the CPU by offloading computationally intensive Model-based HW/SW inline IPSec microarchitectural design and validation using Intel® CoFluentTM Studio Model-based HW/SW inline IPSec microarchitectural design and validation 2 tasks of the IPSec protocol to our network interface controller (NIC). In this white paper, a team of Intel networking engineers presents a flow used to design the microarchitecture of a new 50 Gbps (inline) module in a NIC for Intel® chipsets. This flow is based on models captured using the Intel® CoFluentTM Studio (CoFluentTM) system-level modeling and simulation toolset.